1. Field of the Invention
The present invention relates to supporting PCI Express. In one example, the present invention relates to methods and apparatus for implementing interface circuitry allowing PCI Express cores to operate with a transceiver not compatiable with PCI Express.
2. Description of Related Art
PCI Express is a low-cost, scalable, switched, point-to-point, serial I/O interconnection scheme that maintains backward compatibility with PCI. PCI Express provides a number of benefits over existing bus standards, including increased bandwidth availability and support for real-time data transfer services. PCI Express provides quality of service, power management, and I/O virtualization features. Quality of service and power management improve data integrity and allow control of power consumption. I/O virtualization allows data to be routed along logical routes, permits allocation of bandwidth to groups of devices, and provides the ability to prioritize traffic streams.
Although PCI Express is expected to gain wider acceptance, adoption may be gradual as a large number of existing devices are configured for use with PCI and not PCI Express. For example, programmable chips are often configured with hard-coded transceivers that are not fully compatible with PCI Express. Although PCI Express intellectual property cores may be available to handle link layer operations and higher layer operations, the cores can not necessarily operate with a transceiver does not support PCI Express. Also some Application Specific Standard Products (ASSPs) and Application Specific Integrated Circuits (ASICs) that have some programmability may also include transceiver circuitry that does not fully support PCI Express.
Consequently, it is desirable to provide improved techniques and mechanisms for providing PCI Express support for transceivers that are not fully compatible with PCI Express.